Flashcards

It carries out arithmetic operations (such as addition and subtraction), logical operations (such as AND and OR) and comparisons. Results are usually stored in the accumulator.

It decodes instructions and sends control signals to coordinate the other parts of the processor, memory and I/O, managing the fetch-decode-execute cycle.

The address of the next instruction to be fetched.

The address of the memory location that is about to be read from or written to.

The data or instruction that has just been read from memory, or that is waiting to be written to memory.

The instruction currently being decoded and executed, split into its opcode and operand.

The address bus is one-way (processor to memory). The data bus and control bus are two-way.

It doubles the number of memory locations that can be addressed, because n lines can carry 2ⁿ different addresses.

The address in the PC is copied to the MAR and the PC is incremented. The instruction at that address is sent along the data bus to the MDR, then copied into the CIR.

Only tasks that can be split into parts that run in parallel benefit, and the cores must spend time coordinating and sharing data.

Cache is small, fast memory close to the processor that stores frequently used instructions and data, so they can be fetched much more quickly than from main memory.

Pipelining overlaps the fetch, decode and execute stages of different instructions. After a branch, the instructions already in the pipeline may be the wrong ones, so the pipeline is flushed and refilled.

Von Neumann stores instructions and data in one shared memory with one set of buses. Harvard uses separate memories and buses for instructions and data, so both can be accessed at the same time.

The result of the most recent calculation done by the ALU. Values are loaded into it to be worked on, and stored back to memory from it.

The operand 40 is copied into the MAR and sent along the address bus, with a read signal on the control bus. The value stored at address 40 comes back along the data bus into the MDR, then is copied into the ACC.

The number of clock cycles the processor completes per second, measured in hertz (e.g. 3.5 GHz). Each step of the fetch-decode-execute cycle is timed by the clock, so a higher clock speed executes more instructions per second, but produces more heat.

Main memory holds both instructions and data, as in Von Neumann. Inside the processor, the L1 cache is split into separate instruction and data caches, as in Harvard, so an instruction and data can be fetched at the same time.