Quiz

1.1.1 Structure and function of the processor

Which register holds the address of the next instruction to be fetched?
1. Program Counter (PC)
2. Memory Address Register (MAR)
3. Current Instruction Register (CIR)
4. Accumulator (ACC)
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Answer: Program Counter (PC)

The Program Counter always holds the address of the next instruction. Its value is copied into the MAR at the start of the fetch stage, but the MAR can hold the address of data as well as of instructions.
Which of these happens during the fetch stage of the fetch-decode-execute cycle?
1. The contents of the MDR are copied into the CIR
2. The instruction is split into its opcode and operand
3. The ALU adds a value to the accumulator
4. The contents of the ACC are copied into the PC
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Answer: The contents of the MDR are copied into the CIR

The fetched instruction arrives in the MDR and is then copied into the CIR, which completes the fetch. Splitting it into opcode and operand is part of decoding, and ALU calculations happen during execute.
A processor's address bus is widened from 16 lines to 32 lines. What is the effect?
1. The number of addressable memory locations rises from 2¹⁶ to 2³²
2. The number of addressable memory locations doubles
3. Twice as many bits can be transferred to the processor in each operation
4. The processor's clock speed doubles
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Answer: The number of addressable memory locations rises from 2¹⁶ to 2³²

Each extra address line doubles the number of possible addresses, so going from 16 to 32 lines multiplies it by 2¹⁶, not 2. The number of bits moved per transfer depends on the data bus, not the address bus.
Why might a program run only slightly faster on a quad-core processor than on a single-core processor with the same clock speed?
1. Most of the program cannot be split into tasks that run in parallel
2. Each core runs at a quarter of the clock speed
3. All four cores must share a single Program Counter
4. Only one core can use the ALU at a time, so the others wait
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Answer: Most of the program cannot be split into tasks that run in parallel

Extra cores only help with work that can be divided up and run at the same time. If most of the program must run in sequence, only one core does useful work. Each core is a complete processing unit with its own ALU, control unit and registers, including its own Program Counter.
In a pipelined processor, what normally happens after a branch instruction changes the Program Counter?
1. The instructions already fetched and decoded are discarded and the pipeline is refilled
2. The pipeline carries on, because instructions are always executed in the order they were fetched
3. The processor stops pipelining until the program finishes
4. The branch is ignored until the pipeline is empty
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Answer: The instructions already fetched and decoded are discarded and the pipeline is refilled

The instructions already in the pipeline were fetched from the addresses that follow the branch instruction in memory, so they may be the wrong ones. The pipeline is flushed and filled again from the new address, which costs some cycles.
Which statement describes Harvard architecture?
1. Instructions and data are held in separate memories with separate buses
2. Instructions and data share one memory and one set of buses
3. Several processor cores share one level of cache
4. Instructions are stored in cache and data is stored in registers
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Answer: Instructions and data are held in separate memories with separate buses

Harvard architecture keeps instructions and data in separate memories, each with its own buses, so an instruction and a piece of data can be accessed at the same time. A single shared memory describes Von Neumann architecture.
The instruction BRA 12 is being executed. Which register does the execute stage change?
1. The Program Counter (PC), which is set to 12
2. The Accumulator (ACC), which is set to 12
3. The Memory Data Register (MDR), which receives the value stored at address 12
4. The Current Instruction Register (CIR), which is cleared
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Answer: The Program Counter (PC), which is set to 12

A branch works by overwriting the Program Counter with the target address, so the next fetch comes from address 12 instead of the next instruction in sequence. It does not load or change any data, so the ACC and MDR are not affected.
A processor stores each instruction in a 24-bit word: 8 bits for the opcode and 16 bits for the operand, which holds a memory address. What are the limits of this format?
1. Up to 256 different instructions and 65 536 directly addressable memory locations
2. Up to 8 different instructions and 16 directly addressable memory locations
3. Up to 256 different instructions and 65 535 directly addressable memory locations
4. Up to 16 777 216 different instructions and 65 536 directly addressable memory locations
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Answer: Up to 256 different instructions and 65 536 directly addressable memory locations

With n bits there are 2ⁿ different patterns. The 8-bit opcode allows 2⁸ = 256 instructions, and the 16-bit operand allows 2¹⁶ = 65 536 addresses, numbered 0 to 65 535. The highest address is 65 535, but counting address 0 gives 65 536 locations. Only the opcode bits limit the number of instructions, not the whole 24-bit word.