Quiz
1.4.3 Boolean algebra
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How many rows does a truth table need for a logic circuit with three inputs?
Show answer
Answer: 8
Each input can be 0 or 1, so three inputs give 2 × 2 × 2 = 23 = 8 combinations, one row for each.
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Which expression is equivalent to
¬(A ∧ B)?Show answer
Answer:
¬A ∨ ¬BBy De Morgan's law, negating an AND gives an OR of the negated terms: change the operator and negate each term.
¬A ∧ ¬Bnegates the terms but keeps the operator, which is a common mistake; it is equivalent to¬(A ∨ B)instead. -
Simplify
(A ∨ B) ∧ (A ∨ ¬B).Show answer
Answer:
ADistribution takes out the common
A:A ∨ (B ∧ ¬B).B ∧ ¬Bis always 0, so this becomesA ∨ 0, which isA. The output is 1 exactly whenAis 1, whateverBis. -
A half adder has inputs
A= 1 andB= 1. What are its outputs?Show answer
Answer: Sum = 0, Carry = 1
In binary 1 + 1 = 10. The sum is
A ⊻ B, which is 0 when both inputs are 1, and the carry isA ∧ B, which is 1. -
The data input
Dof a D-type flip-flop changes from 0 to 1 between two rising edges of the clock. What happens to the outputQ?Show answer
Answer:
Qkeeps its previous value until the next rising edge of the clockA D-type flip-flop only copies
DtoQon the rising edge of the clock. Between edges,Qholds whatever it stored last, which is what lets it act as one bit of memory. Changing value on every clock edge describes a different circuit, a toggle. -
When simplifying with a Karnaugh map, why can three neighbouring 1s in a row not form a single group?
Show answer
Answer: Groups must contain a power-of-two number of cells: 1, 2, 4, 8 or 16
Only groups of 1, 2, 4, 8 or 16 cells correspond to a single simplified term, because each doubling of the group size removes one variable from the term. Three 1s in a row are covered by two overlapping pairs. Groups can be long rectangles as well as squares, and they may wrap around the edges.
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A plant-watering pump (
P) switches on when the soil is dry (S) and either the timer has run out (R) or the manual button is pressed (M). Which expression describes this?Show answer
Answer:
P ≡ S ∧ (R ∨ M)The pump needs dry soil in every case, so
Sis joined by AND to the whole of the second condition. "Either the timer or the button" isR ∨ M, and the brackets make sure it is worked out first. Without them,(S ∧ R) ∨ Mwould run the pump whenever the button is pressed, even in wet soil. -
For
Q ≡ (A ∧ B) ∨ ¬C, which set of inputs makesQfalse?Show answer
Answer:
A= T,B= F,C= TQis false only when both parts of the OR are false:A ∧ Bmust be false and¬Cmust be false, soCmust be true. WithA= T,B= F andC= T,A ∧ Bis F and¬Cis F, soQis F. In the other sets, either bothAandBare true orCis false, which makesQtrue. -
What is the simplest expression for this Karnaugh map?
BC= 0001 11 10 A= 01 0 0 1 A= 10 0 1 1 Show answer
Answer:
(¬A ∧ ¬C) ∨ (A ∧ B)In the
A= 0 row, the 1s atBC= 00 andBC= 10 are neighbours because the map wraps around;Ais 0 andCis 0 in both, giving¬A ∧ ¬C. In theA= 1 row, the 1s at 11 and 10 pair up;AandBare 1 in both, givingA ∧ B. These two pairs cover every 1. Grouping the 00 and 10 columns together as¬Cwould include the 0 atA= 1,BC= 00. Adding a third pair down the 10 column is not wrong, but it is not the simplest, because those 1s are already covered. -
A full adder has inputs
A= 1,B= 1 and carry inCin= 1. What are its outputs?Show answer
Answer: Sum = 1, Carry out = 1
Adding three 1s gives three, which is 11 in binary. The sum bit is the right-hand 1 and the carry out is the left-hand 1. Using the expressions,
S ≡ A ⊻ B ⊻ Cinis 1 because an odd number of inputs are 1, andCoutis 1 becauseA ∧ Bis 1. -
A D-type flip-flop holds
Q= 0.Dchanges to 1 while the clock stays low. What isQnow?Show answer
Answer: 0
Qonly takes the value ofDon a rising edge of the clock. Until the clock rises,Qholds its old value, 0, howeverDchanges. -
In a full adder built from two half adders, what joins the two half adders' carry outputs to give the carry out?
Show answer
Answer: An OR gate
There should be a carry out if either half adder produces a carry, so the two carries go into an OR gate. An AND gate would only carry when both did, and a NAND gate would give a carry out when neither half adder carries.