Exam questions: Structure and function of the processor

Question 1

8 marks

1(a) 4 marks

The stored program concept uses the Fetch-Decode-Execute cycle to get the next instruction from memory and then execute it.

Describe what happens during the fetch stage of the Fetch-Decode-Execute cycle.

You should state the different registers and buses that are used in your answer.

Your answer

Mark scheme 1(a)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

1 mark per bullet to max 4:

The contents of the Program Counter/PC are copied/sent to the Memory Address Register/ MAR
The address is sent/transferred along the address bus
The control unit sends/transfers a (read) signal along the control bus
Contents stored in the memory address are sent/transferred along the data bus
Contents (from memory) are stored in the Memory Data Register/MDR
...and sent/copied to the Current Instruction Register/ CIR
The Program Counter/PC is incremented

Guidance

Accept IR/Instruction Register for CIR/Current instruction Register

Accept MBR/Memory Buffer Register for MDR/Memory Data Register

Examiner’s Comments

Candidates who had good knowledge of the FDE cycle were able to gain 3 or 4 marks on this question. Some candidates did not have a good understanding of what a register or a bus is and tended to say they did something other than transport or temporarily store. Many however gave clear and correct responses.

[An examiner's marking symbol, not shown here.]

Misconception

Some candidates gave responses which mentioned a register fetching the data or passing data. A register is a temporary store for
data/instructions/addresses and as such doesn’t fetch or pass anything.

Exemplar 1

[Image redrawn from the original mark scheme by an AI model (Gemma 4 12B). It may contain mistakes.]

A candidate's handwritten answer:

The PC holds the next instruction's address which is copied to the MAR memory address register. The Program Counter is incremented. The address from the MAR is sent on the address bus to main memory. Simultaneously a read/write signal is sent on the control bus to the control unit. The data or instruction goes on the data bus and is copied into the memory data register. It is then copied into the CIR. [4]

This candidate has shown a clear understanding of the role of the buses and registers in the fetch part of the FDE cycle.

Your mark for 1(a)

out of 4

1(b) 1 mark

One of the instructions that may be fetched and executed as part of this cycle is a branch instruction.

State the name of the register that would be altered in the execute phase during a branch instruction.

Your answer

Mark scheme 1(b)

Program Counter / PC

Guidance

Examiner’s Comments

Candidates who understood the FDE

cycle gained the mark. Those that did not tended to mention a register used in the fetch or decode stages.

1(c) 3 marks

Three ways of improving the performance of a CPU are increasing the clock speed, adding more cores and using pipelining.

Explain how pipelining improves the performance of a CPU.

Your answer

Mark scheme 1(c)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

1 mark per bullet:

Allows the next instruction to be fetched whilst the previous one is being decoded/executed /allows the overlapping of different parts of the FDE
It increases throughput / increases the number of instructions processed in a set period of time
It prevents the CPU having to wait / prevents idle components

Guidance

DNA responses that talk about the FDE running faster.
Allow a diagram demonstrating pipelining for MP1.

Allow ‘it will take less time to do the same amount of instructions’ for MP2

BOD ‘processes’ for ‘instructions’ for MP2.
DNA ‘more efficient’ on its own for MP2

DNA points if clearly discussing multiple cores.

Examiner’s Comments

Many candidates were able to gain a mark for an instruction being fetched at the same time as another is decoded. Some candidates discussed multiple cores which were mentioned in the question stem but did not apply to this question. Candidates should have access to previous mark schemes.

Your mark for 1(c)

out of 3

Question 2

5 marks

2 5 marks

Here is a diagram of a computer system.

[Diagram redrawn from the original paper by an AI model (Gemma 4 12B). It may contain mistakes.]

The image shows a block diagram of a computer system architecture. At the top are three horizontal buses: "Control Bus", "A" (Data Bus), and "Address Bus". Below these is a "CPU" block containing a "Control Unit" (with components B, C, D, CIR, and a "+1" incrementer) and an "ALU" (Arithmetic Logic Unit) with an "E" register. To the right of the CPU is a "RAM" block. Various arrows indicate the flow of data and control signals between the buses, the CPU components, and the RAM.

Identify each of the labelled components in this computer system.

A
B
C
D
E

Your answer

Mark scheme 2

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

1 Mark for each labelled component.

A	Data Bus
B	MAR / Memory Address Register
C	PC / Program Counter
D	MDR / Memory Data Register
E	ACC / Accumulator

Guidance

Accept MBR / Memory Buffer Register for D

Examiner’s Comments

This question was generally answered well. Most candidates were able to identify the data bus, Memory Address Register (MAR) and Memory Data Register (MDR), although some candidates were not able to identify the Program Counter (PC) and/or the Accumulator (ACC).

Your mark for 2

out of 5

Question 3

9 marks

3 9 marks

Most modern computers are designed using Von Neumann Architecture. However, in some cases Harvard Architecture may be preferred.

Discuss the difference between Von Neumann Architecture and Harvard Architecture.

You should refer to the following in your answer:

the different approaches each architecture takes to storing instructions and data
the benefits of using a Von Neumann Architecture approach
the benefits of using a Harvard Architecture approach.

Your answer

Mark scheme 3

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Mark Band 3- High Level
(7-9 marks)
The candidate demonstrates a thorough knowledge and
understanding of both Von Neumann

and Harvard architectures.
All detail is generally accurate and relevant.
The candidate is able to apply their knowledge and understanding directly and consistently to the context provided.
Evidence/examples will be explicitly relevant to the explanation. The candidate will come to a clear conclusion that must be justified by their comments.

There is a well-developed line of reasoning which is clear and logically structured. The information presented is relevant and substantiated.

Mark Band 2- Mid Level
(4-6 marks)
The candidate demonstrates reasonable knowledge and
understanding of Von Neumann and Harvard architectures; the material is generally accurate but at times underdeveloped. The candidate may not have applied both to this scenario. The candidate is able to apply their knowledge and understanding directly to the context provided although one or two opportunities are missed. Evidence/examples are for the most part implicitly relevant to the explanation.
The candidate will attempt to come to a conclusion, although it may not be fully justified by their answer.

There is a line of reasoning presented with some structure. The information presented is in the most part relevant and supported by some evidence.

Mark Band 1- Low Level
(1-3 marks)
The candidate demonstrates a basic knowledge of Von Neumann and Harvard architectures. The material is basic and contains some
inaccuracies.
The candidate makes a limited attempt to apply acquired knowledge and understanding to the context provided.

The candidate provides nothing more than an unsupported assertion.

The information is basic and communicated in an unstructured way. The information is supported by limited evidence and the relationship to the evidence may not be clear.

0 mark
No attempt to answer the question or response is not worthy of credit.

Guidance

AO1
Harvard Architecture:

Uses separate memory for data and instructions.
Uses separate data and address buses for each piece of memory
Can read/write data and instructions simultaneously

Von Neumann Architecture:

Uses one physical piece of memory for both data and instructions
Uses one data and one address bus.
Can only read/write data or instructions, not both at the same time

AO2

Von Neumann design is less complex. Development of one is cheaper. Harvard design is more complex as it requires two buses. Development is more expensive. More CPU pins are required; a complex motherboard is required with doubling of memory.
Harvard Architecture free data memory cannot be used for instructions and vice-versa

AO3

Harvard architecture allows for faster processing as instructions and data are simultaneously fetched/executed.
Harvard splits memory between instruction and data in a static way, meaning you could run out of one memory with unused memory in the other area.
Von Neumann architecture allows for dynamic allocation between instruction and data
Large programs with small data (Computer games) or small programs with large data (video editing) can be equally catered for

Examiner’s Comments

Candidates were assessed on the quality of their extended response in this question. Most of the candidates were clear on the basic difference between Harvard and Von Neumann architecture, but many did not discuss this in detail or did not use the correct terminology. Some candidates confused the different architectures and contradicted points in their discussion.

Exemplar 1

[Image redrawn from the original mark scheme by an AI model (Gemma 4 12B). It may contain mistakes.]

A candidate's handwritten answer:

Von Neumann and Harvard store data in different ways. They both have separate memory and address buses, however Harvard has separate memory locations for data and instruction while Von Neumann stores all both in the same memory.

Von Neumann is good as it allows for [unclear] writing programs to be run off. A memory is joint, data and instructions can split memory in an efficient way, reducing bottlenecks to the same full like it can happen in Harvard architecture. Also, Von Neumann host programs are written to support a Von Neumann architecture therefore it's easier to set up and use has it has more support from developers. Better for multi-purpose systems.

Harvard is less complex and memory management is simpler. It's good for custom programs as it can run faster if code is written specifically. Very good for embedded systems in which structure can't change. In conclusion they're both useful while Von Neumann is more widely used and better for general purpose computers, Harvard architecture can be good for more simple and specific cases, such as embedded systems, or machines which do not need a general purpose CPU, &

This candidate response was given 5 marks. There are some valid points about both Von Neumann and Harvard Architecture, but the points made are not fully developed with limited application. This response was therefore given a mark within the mid- level band.

[An examiner's marking symbol, not shown here.]

Assessment for learning

Questions with the command word ‘discuss’ require candidates to give a balanced discussion and provided a suitable conclusion which justifies their comments. Opportunities to practise these questions will support candidates to do better on these style questions.

Your mark for 3

out of 9

Question 4

4 marks

4 4 marks

OCRSystems are designing a new CPU for a computer system that will be used for video rendering. Part of the video rendering process is when the video is exported. This is when the computer combines all of the separate video elements together to form the final video.

Describe two factors that affect the performance of the CPU.

1

2

Your answer

Mark scheme 4

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Clock Speed …
… The speed at which the fetch decode execute cycle is completed/ the speed a single core can execute instructions
Number of cores/ independent processing units …
…that can fetch decode execute at the same time
Cache size…
… memory that contains recently/frequently used instructions/data
…memory that has a faster R/W speed than RAM
…memory that is closer to/onboard the CPU

Guidance

One mark for stating the factor, mark for expanding the factor

Accept cycles for “FDE Cycles”

Examiner’s Comments

Most candidates were able to identify two factors that could affect the performance of the CPU, but many were not given all 4 marks as they did not fully describe why each factor would affect the performance. See Exemplar 1, which was given full marks.

Exemplar 1

[Image redrawn from the original mark scheme by an AI model (Gemma 4 12B). It may contain mistakes.]

A candidate's handwritten answer:

Clock Speed, the number of clock cycles that occur per second (in Hertz). The higher the clock speed the more data/instructions executed within a given time frame, increasing performance.

The number of cores, the more number of cores a processor has, the more FDE cycles can be conducted simultaneously, so more data instructions are executed at one point, increasing performance.

The candidate gives two valid factors that would affect performance and then explains why each of the two factors would affect performance. They use appropriate terminology in their response.

Your mark for 4

out of 4

Question 5

12 marks

5(a) 2 marks

A charity is concerned that the performance of a computer is not sufficient and wishes to replace the processor.

Give two features of a replacement processor that would increase the typical performance of the computer.

1

2

Your answer

Mark scheme 5(a)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Higher/faster clock speed
More cores/dual/quad/etc core
More cache memory.

Guidance

Answers must refer to an
improvement (more/higher/faster) not just “change the clock speed” Allow discussions of level 1/level 2 cache

sizes for one mark.

Accept valid features of CPUs that would improve performance e.g. Use of:
Pipelining
Simultaneous Multithreading Do not accept RISC/CISC.

Examiner’s Comments
Most candidates were able to gain full marks on this question. Less successful responses often mentioned clock speed, cache or cores without referring to an improvement, e.g. higher or faster.

Your mark for 5(a)

out of 2

5(b)

The processor contains registers including the accumulator and the program counter. The contents of these registers are modified during the Fetch-Decode-Execute cycle.

5(b)(i) 2 marks

Describe how the accumulator is used during the Fetch-Decode-Execute cycle.

Your answer

Mark scheme 5(b)(i)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Holds all input/output
Holds results of calculations (from the ALU)
Checked for conditional branching (e.g. BRZ)
Stores data which has come from the MDR/RAM

Guidance

Examiner’s Comments
Most candidates were able to access 1 mark for the result of ALU calculations, but few were able to give two uses. Some confused the accumulator with the program counter and the ALU.

Your mark for 5(b)(i)

out of 2

5(b)(ii) 2 marks

Describe how the program counter is used during the Fetch-Decode-Execute cycle.

Your answer

Mark scheme 5(b)(ii)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Holds the address/location of the next instruction (to be executed/fetched)
Contents copied to the MAR at start of FDE
Incremented (by one) on every cycle
Can be changed by branch/jump instructions

Guidance

Examiner’s Comments
This question was generally well answered by candidates who gave clear responses.

Misconception
Some candidates thought that the program counter kept track of a count of the number of instructions that had been fetched.

[An examiner's marking symbol, not shown here.]

Your mark for 5(b)(ii)

out of 2

5(b)(iii) 3 marks

State the name of three other registers that are used during the Fetch-Decode-Execute cycle.

1

2

3

Your answer

Mark scheme 5(b)(iii)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Memory Address Register / MAR
Memory Data Register / MDR
Current Instruction Register / CIR
Index Register / IR

Guidance

Allow Memory Buffer Register for MDR

Examiner’s Comments
Most candidates gained full marks on this question and were able to correctly identify three other registers. Some lost marks for saying the ALU or control unit were registers.

Your mark for 5(b)(iii)

out of 3

5(c)

A charity uses a desktop computer to record financial donations that it receives. The computer contains a single core, 2.4GHz processor with 2MB cache.

A processor uses the Von Neumann architecture.

5(c)(ii) 1 mark

Give one way that the Harvard architecture differs from the Von Neumann architecture.

Your answer

Mark scheme 5(c)(ii)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Separate memory for data and instructions / Multiple memory units
Different (sets of) buses one for instructions & one for data/ instructions and data can be accessed concurrently.

Guidance

Examiner’s Comments
This question was generally answered well by candidates and the majority gave separate areas of memory for data and instructions. Where candidates were not given marks, it was generally because their answer was unclear, e.g. just saying ‘separate memory’.

Your mark for 5(c)(ii)

out of 1

Question 6

1 mark

6 1 mark

State why computer systems store data in binary.

Your answer

Mark scheme 6

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

1 mark for any of the following bullet points, e.g:

Computers use binary logic for on/off or 1/0
Computer systems are based on switches/transistors
Binary is high tolerance

Guidance

Examiner’s Comments
This question was generally answered well.

Your mark for 6

out of 1

Question 7

4 marks

7

Different computing devices in Arnold’s home use different processor architectures.

One processor architecture is the Harvard architecture.

7(i) 2 marks

Describe the Harvard architecture.

Your answer

Mark scheme 7(i)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

1 mark per bullet up to a maximum of 2 marks, e.g:

Uses separate memory blocks for instructions and data
Has separate buses (data and address) for data and instructions
Has fixed memory sizes for data and Instructions
Instruction memory may be ROM

Guidance

Accept unit instead of blocks (BP1)

Examiner’s Comments
Some candidates were vague in their response and were not clear that Harvard has separate memory blocks. Candidates must be specific in their response.

Your mark for 7(i)

out of 2

7(ii) 2 marks

Arnold has a smart washing machine.

Explain why the Harvard architecture is suitable for a device like this.

Your answer

Mark scheme 7(ii)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

1 mark per bullet up to a maximum of 2 marks, e.g:

Fixed instruction size
No need for memory to be shared between data and instructions
Removes need for secondary storage
Instructions would never be changed

2 (AO2.1) (2) Any 2 (Max 2)

Guidance

Examiner’s Comments
This question was not answered well. Many candidates repeated their response to the previous question and did not answer the question correctly. Candidates need to read questions carefully.

Your mark for 7(ii)

out of 2

Question 8

4 marks

8

A program written using the Little Man Computer instruction set is shown in Fig. 1.

[Diagram redrawn from the original paper by an AI model (Gemma 4 12B). It may contain mistakes.]

        INP
        STA  numone
        INP
        STA  numtwo
main     LDA  numone
        SUB  numtwo
        BRP  pos
notpos   LDA  count
        OUT
        LDA  numone
        OUT
        HLT
pos       STA  numone
        LDA  count
        ADD  one
        STA  count
        BRA  main
numone    DAT
numtwo    DAT
one       DAT  1
count     DAT  0

Fig. 1

In Von Neumann Architecture, various registers are used when a program is executed.

8(i) 2 marks

State what is meant by the term ‘register’.

Your answer

Mark scheme 8(i)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Temporary storage/memory location…
…inside the CPU
Used for a single specific purpose
Faster access speed than RAM / secondary storage

Your mark for 8(i)

out of 2

8(ii) 2 marks

Explain how the accumulator is used when the line BRP pos is executed.

Your answer

Mark scheme 8(ii)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Accumulator checked to see if value held is positive or zero
If so, BRANCH carried out / jumps to specified location.

Your mark for 8(ii)

out of 2

Question 9

11 marks

9(a) 3 marks

The CPU uses pipelining to improve efficiency.

Explain what is meant by the term ‘pipelining’.

Your answer

Mark scheme 9(a)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Concurrent processing of multiple instructions
One instruction can be fetched while previous isbeing decoded…
And the one before is being executed.
In case of a branch pipeline is flushed.
Increases speed of execution

Your mark for 9(a)

out of 3

9(b)

OCR Insurance uses a computer system to calculate the price that customers pay for car insurance.

The computer system contains a CPU, GPU, RAM and ROM.

9(b)(i) 2 marks

State two factors that affect the performance of a CPU.

1

2

Your answer

Mark scheme 9(b)(i)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Clock speed
Number of cores
Cache

Guidance

Accept
Use of pipelining/size of pipeline Use of out of order execution Use of SIMD instructions
Integrated graphics processing on CPU

Your mark for 9(b)(i)

out of 2

9(b)(ii) 4 marks

Explain the difference between RAM and ROM, including how these are used by the computer system.

Your answer

Mark scheme 9(b)(ii)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

RAM is volatile
Used for storing programs/data/parts of OS currently in use
ROM is non volatile
Used for storing (e.g.) BIOS / bootstrap

Your mark for 9(b)(ii)

out of 4

9(b)(iii) 2 marks

Describe one non-graphical use for a GPU.

Your answer

Mark scheme 9(b)(iii)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Performing complex numerical calculations
Calculations on matrices / vectors / multiple data atthe same time
…e.g. insurance pricing, modelling risk, calculating bills

Guidance

Example has to relate to insurance company

Your mark for 9(b)(iii)

out of 2

Question 10

6 marks

10(a) 4 marks

Amy’s processor makes use of pipelining during the fetch-decode-execute cycle.

The processor’s pipeline consists of the following stages:

Fetching the instruction from memory
Decoding the instruction
Executing the instruction.

Instructions A, B, C and D need to be processed.

Identify the stage(s) and instruction(s) run during each pipeline below.

Pipeline 1

Pipeline 2

Pipeline 3

Pipeline 4

Your answer

Mark scheme 10(a)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

1 mark for each interval

Interval 1

A is fetched

Interval 2

A is decoded
B is fetched

Interval 3

A is executed
B is decoded
C is fetched

Interval 4

B is executed
C is decoded
D is fetched

Your mark for 10(a)

out of 4

10(b) 2 marks

Explain why pipelining can improve the performance of the processor.

Your answer

Mark scheme 10(b)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

1 mark per bullet up to a maximum of 2 marks:

Reduces/removes latency
… CPU is not idle while waiting for next instruction
Next instruction is fetched while current one is decoded/executed
All parts of the processor can be used at any instance in time.

Your mark for 10(b)

out of 2

Question 11

11 marks

11(a) 5 marks

The table below shows the Little Man Computer instruction set.

Mnemonic	Instruction
`ADD`	Add
`SUB`	Subtract
`STA`
`LDA`	Load
	Branch always
`BRZ`
`BRP`
`INP`	Input
`OUT`	Output
	End program

Complete the table above to show the missing mnemonics and instructions.

Your answer

Mark scheme 11(a)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Store value in accumulator at address given
BRA / BR
Branch if zero
Branch if zero or positive
HLT / COB / END

Guidance

[Image redrawn from the original mark scheme by an AI model (Gemma 4 12B). It may contain mistakes.]

Mnemonic	Instruction
ADD	Add
SUB	Subtract
STA	Store value in accumulator at address given
LDA	Load (to accumulator)
BRA	Branch always
BRZ	Branch if zero
BRP	Branch if zero or positive
INP	Input
OUT	Output
HLT	End program

Your mark for 11(a)

out of 5

11(b) 6 marks

Write a program using the Little Man Computer instruction set that will allow a user to input two numbers and then output the larger of the two numbers. The program should loop continuously.

Your answer

Mark scheme 11(b)

Tick each point your answer makes. Your mark is worked out from your ticks, and you can change it.

Inputs two numbers
..stores at least one of them
Comparison / subtraction to decide which is larger
Jump / output if num1 larger
Jump / output if num2 larger or nums equal
Loops back to start after either output

Guidance

Example answer
start INP
STA x
INP
STA y
SUB x
BRP first
LDA x
OUT
BRA start
first LDA y
OUT
BRA start
x DAT
y DAT

Your mark for 11(b)

out of 6

Question 12

7 marks

12(b)

A CPU will repeatedly run the Fetch-Decode-Execute-cycle shown in Fig. 1.

[Diagram redrawn from the original paper by an AI model (Gemma 4 12B). It may contain mistakes.]

stateDiagram-v2
    Fetch --> Decode: A
    Decode --> Execute: B
    Execute --> Fetch: C

Fig. 1

12(b)(i) 4 marks

Describe what happens during the ‘Fetch’ stage shown in Fig. 1.

You should refer to the use of specific registers in your answer.

Your answer

Your mark for 12(b)(i)

out of 4

12(b)(ii) 1 mark

A CPU may need to stop running the Fetch-Decode-Execute-cycle in order to handle an interrupt.

Tick one box to indicate where in Fig. 1 an interrupt would be handled.

A

B

C

END OF QUESTION PAPER

Your answer

Your mark for 12(b)(ii)

out of 1